I'm Michael Rowlands. I'm a Signal Integrity Engineer by trade (since 1998) and a systems engineer at heart. I like to observe, learn and improve systems by developing a good process and then automate that process with excellent tools and an elegant workflow. SI is just a system to get a signal from point A to point B, through a channel with many pieces. My engineering philosophy is to make work simple ! Let people do the creativity and critical decisions that we are good at, and let computers do the calculations and repeated tasks that they are good at.
Please connect with me on LinkedIn!
https://www.linkedin.com/in/michael-rowlands-9a22a312/
For more information on my background, here's a summary of my CV. (a summary of a summary?)
I've been a Signal Integrity Engineer for about 19 years now. I'm currently designing connectors and cables and cable assemblies in the high-speed IO group at Amphenol. In 2016, I worked in the TempFlex Cable group at Molex; designing twin-ax and co-ax cables for 50GHz/112Gbps signaling. I specialize in signal integrity at multi-gigahertz frequencies. I received a Bachelor's and Master's degree in Electrical Engineering from MIT in 1998. Upon graduation, I worked four years as a signal integrity engineer at Teradyne in Boston. I designed cable assemblies, circuit boards and interconnects for test equipment up to 6 GHz. In 2002, I worked at a startup company in Illinois. The company designed dispersion compensation microchips at 12.5 Gbps for fiber-optic communications. I designed circuit boards to demonstrate and verify 12.5Gbps performance and made algorithm improvements based on system modeling. In 2005, as part of the Research and Development at Endicott Interconnect Technologies, I designed and analyzed circuit boards, chip packages and custom computing systems. Starting in 2009, he worked at Molex designing next-generation 25-40Gbps I/O and board-to-board connectors.
AWARDS and PATENTS
Won the Molex Innovation Challenge business competition in 2015, using Carbon Nanotubes for electronics products
DesignCon Best Paper Award in 2014 for “Quantitative EMI Analysis of Electrical connectors Using Simulation Models.”
High density connector, Patent US 9385455 B2
High density connector, Patent US 9525245 B2
Connector with tuned terminal beam, Patent US 9660383 B2
Liquid crystal polymer layer for encapsulation and improved hermiticity of circuitized substrates, Patent US 8143530 B1
Differentially coupled connector, Patent US 9515421 B2
Circuitized substrate with internal resistor, method of making said circuitized substrate US 20080087459 A1
PUBLICATIONS
Correia, D. Haser, A. and Rowlands, Michael, “GSSG Resonance Method for Interconnect Designs” signalintegrityjournal.com, June 2017.
DeAraujo, D. Filip, C. Guruswamy, P. and Rowlands, Michael, “Optimization Methods for High Speed SerDes Channels Using COM Metric”, Proc. DesignCon, January 27-30, 2017, San Jose, CA.
Rowlands, Michael, Li, X. and Bhobe, A., “EMI Analysis of High-Speed I/O Connectors in an Active System”, Proc. DesignCon, January 27-30, 2015, San Jose, CA.
Park, IL-Young, Rowlands, M., and Quach, M., “QSFP28 Connector Footprint Optimization of
Crosstalk and ILD_rms_dB for 25+ Gbps Signaling”, Proc. EMI/SIPI, March, 2015, San Jose, CA.
Rowlands, Michael, Li, X. and Bhobe, A., “EMI Analysis of High-Speed I/O Connectors in an Active System”, Proc. DesignCon, January 27-30, 2015, San Jose, CA.
Rowlands, Michael, Correia, D., and Park, IL., “What Makes a Good Channel? COM vs. BER Metrics”, Proc. DesignCon, January 27-30, 2015, San Jose, CA.
Rowlands, Michael, Bhobe, A., Casher, P and Li, X., “Quantitative EMI Analysis or Electrical Connectors Using Simulation Models”, Proc. DesignCon, February 1-3, 2014, San Jose, CA.
RECEIVED BEST PAPER AWARD DESIGNCON 2014
Rowlands, Michael, Patel, Pravin and Casher, Patrick, “System Performance as a Function of Common Mode Metrics”, Proc. DesignCon, February 1-4, 2012, San Jose, CA.
Das, R., Lauffer, J., and Rowlands, M., “Enabling High-Performance RF Designs Using Z-Interconnect: Materials, Manufacturing and Electrical Performance”
Proc. MILCOM, November 17-19, 2009, San Diego, CA.
Huang, J. and Rowlands, M., “How Long is Too Long? A Via Stub Electrical Performance Study”, Proc. DesignCon, February 2-5, 2009, San Jose, CA.
Das, Rabindra and Rowlands, Michael, “Manufacture and Ultra-High Frequency Performance of an LCP-Based, Z- Interconnect, Flip-Chip Package”, Proc. Electronic Components and Technology Conference, May 27-30, 2008, Orlando, FL.
Rowlands, Michael, "Manufacture and Performance of a Z-interconnect HDI Circuit Card", Proc. IPC-APEX, April 1-3, 2008, Las Vegas, NV.
Rowlands, Michael, "Manufacture and Characterization of a Novel Flip-Chip Package Z-interconnect Stackup with RF Structures", Proc. International Micro-Electronics and Packaging Symposium, November 11-15, 2007, San Jose, CA.
Das, Rabindra and Rowlands, Michael, “Electrical Performance of an Organic, Z-interconnect, Flip-Chip Substrate”, Proc. Electronic Components and Technology Conference, May 29-June 1, 2007, Reno, NV.
Rosser, Steven and Rowlands, Michael, “Simulation and Measurement of High Speed Serial Link Performance in a Dense, Thin Core Flip Chip Package”, Proc. DesignCon East, Sept 19-21, 2005, Worcester, MA.
Lee, M.C., Riddolls, R.J., Vilece, K.D., Dalrymple, N.E., Rowlands, M.J., Moriarty, D.T., Groves, K.M., Suzer, M.P. and Kuo, S.P., “Laboratory Reproduction of Arecibo Experimental Results: HF Wave-Enhanced Langmuir Waves”, Geophysical Research Letters, 24, 115, 1997.
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